In many high performance microprocessor and ASIC designs there exist long conductive lines on which the peak noise must be controlled to ensure adequate noise margin for the receiver of the long line. This problem has traditionally been handled by improving the noise margin of the receiving circuitry at significant performance impact, inserting buffers, or altering the physical geometry of the wires to reduce line to line coupling effects. In many instances, however, there are wiring/floorplan congestions which constrain physical solutions. Therefore, a need exists to route conductive lines next to each other in microelectronic chips for long distances, while maintaining control over the maximum amount of noise coupled between them.